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<a accesskey="3" href="page.php?w=logic_synthesis&amp;p=2">3.Next</a>
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<p>In <a href="page.php?w=computer_engineering">computer engineering</a>, <b>logic synthesis</b> is a process by which an abstract specification of desired <a href="page.php?w=circuit_%28electronics%29">circuit</a> behavior, typically at <a href="page.php?w=register_transfer_level">register transfer level</a> (RTL), is turned into a design implementation in terms of <a href="page.php?w=logic_gates">logic gates</a>, typically by a <a href="page.php?w=computer_program">computer program</a> called a synthesis tool. Common examples of this process include</p><p>
<a accesskey="3" href="page.php?w=logic_synthesis&amp;p=2">3.Next</a>
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