<?xml version="1.0" encoding='utf-8'?>
<!DOCTYPE wml PUBLIC "-//WAPFORUM//DTD WML 1.1//EN" "http://www.wapforum.org/DTD/wml_1.1.xml">
<wml>
<card id="card1" title="Logic synthesis - Page 10 - Wikipedia">
<p>
<a accesskey="1" href="page.php?w=logic_synthesis&amp;p=9">1.Previous</a><br />
<a accesskey="3" href="page.php?w=logic_synthesis&amp;p=11">3.Next</a>
</p>
<p>in the standard design cycle in which the <a href="page.php?w=functional_design">functional design</a> of an <a href="page.php?w=electronic_circuit">electronic circuit</a> is converted into the representation which captures <a href="page.php?w=Boolean_algebra_%28logic%29">logic operations</a>, <a href="page.php?w=arithmetic_operations">arithmetic operations</a>, <a href="page.php?w=control_flow">control flow</a>, etc. A common output of this step is <a href="page.php?w=RTL_description">RTL description</a>. Logic design is commonly followed by</p><p>
<a accesskey="1" href="page.php?w=logic_synthesis&amp;p=9">1.Previous</a><br />
<a accesskey="3" href="page.php?w=logic_synthesis&amp;p=11">3.Next</a>
</p>

<do type="prev" label="Search">
        <go href="search.wml"/>
</do>

</card>
</wml>
