<?xml version="1.0" encoding='utf-8'?>
<!DOCTYPE wml PUBLIC "-//WAPFORUM//DTD WML 1.1//EN" "http://www.wapforum.org/DTD/wml_1.1.xml">
<wml>
<card id="card1" title="3 nm process - Page 13 - Wikipedia">
<p>
<a accesskey="1" href="page.php?w=3_nm_process&amp;p=12">1.Previous</a><br />
<a accesskey="3" href="page.php?w=3_nm_process&amp;p=14">3.Next</a>
</p>
<p>density. Since many designs included considerably more SRAM than logic - a common ratio being 70% SRAM to 30% logic = die shrinks were expected to be around 26%. TSMC was planning volume production in the second half of 2022.</p>

<p>In July 2021, Intel presented brand new process <a href="page.php?w=technology_roadmap">technology roadmap</a>, according to which "Intel 3" process (previously named Intel 7+), the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, was scheduled</p><p>
<a accesskey="1" href="page.php?w=3_nm_process&amp;p=12">1.Previous</a><br />
<a accesskey="3" href="page.php?w=3_nm_process&amp;p=14">3.Next</a>
</p>

<do type="prev" label="Search">
        <go href="search.wml"/>
</do>

</card>
</wml>
