bit.
* Hardware mitigations against the Spectre V4 speculative store bypass vulnerability.
* Zero-latency memory mirroring optimization (undocumented).
* Doubled width of the execution units and load store units (from 128-bit to 256-bit) in the floating point coprocessor and significant further throughput enhancements in the multiplication execution unit. This allows the FPU to perform single-cycle AVX2 calculations.
* Introduced CPPC power management.

Feature tables

CPUs

APUs

APU features table

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