in figure) which controls the two access transistors M₅ and M₆ in 6T SRAM figure (or M₃ and M₄ in 4T SRAM figure) which, in turn, control whether the cell should be connected to the bit lines: BL and BL. They are used to transfer data for both read and write operations.

During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM bandwidth compared to DRAMsin a DRAM, the bit line is