<?xml version="1.0" encoding='utf-8'?>
<!DOCTYPE wml PUBLIC "-//WAPFORUM//DTD WML 1.1//EN" "http://www.wapforum.org/DTD/wml_1.1.xml">
<wml>
<card id="card1" title="Penryn (microarchitecture) - Page 3 - Wikipedia">
<p>
<a accesskey="1" href="page.php?w=Penryn_(microarchitecture)&amp;p=2">1.Previous</a><br />
<a accesskey="3" href="page.php?w=Penryn_%28microarchitecture%29&amp;p=4">3.Next</a>
</p>
<p>instructions (some of which are enabled by the new single-cycle shuffle engine).</p>

<p>Maximum L2 <a href="page.php?w=CPU_cache">cache</a> size per chip was increased from 4 to 6 MB, with L2 associativity increased from 16-way to 24-way. <a href="page.php?w=Product_binning">Cut-down versions </a>with 3 MB L2 also exist, which are commonly called Penryn-3M and Wolfdale-3M as well as Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model</p><p>
<a accesskey="1" href="page.php?w=Penryn_(microarchitecture)&amp;p=2">1.Previous</a><br />
<a accesskey="3" href="page.php?w=Penryn_%28microarchitecture%29&amp;p=4">3.Next</a>
</p>

<do type="prev" label="Search">
        <go href="search.wml"/>
</do>

</card>
</wml>
