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Performance

* Initial clock rate at 400 MHz.
* (ODR): Eight bits per clock cycle per lane.
* Each chip provides 8, 16, or 32 programmable lanes, providing up to 230.4 Gbit/s (28.8 GB/s) at 900 MHz (7.2 GHz effective).

Features

* Bi-directional differential Rambus Signalling Levels (DRSL)
** This uses differential open-collector

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