Gen7

* ¹ FP32 ALUs : EUs : Subslices
* Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions.
* Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler,