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*Reset -- initializes all flip-flops to known states, typically '0'. Depending on the register design, this may be synchronous or asynchronous. This is typically used to zero the flip-flops before starting clocked operation.
*Clock -- upon rising or falling signal edge (the active edge), causes the data presented on the data inputs to be stored in the register's flip-flops. In registers that have a synchronous reset input in which reset is asserted, a clock active edge will invoke a register reset in lieu of storing input data.
*Data

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