known as multi-threshold CMOS (MTCMOS). The sleep transistor sizing is an important design parameter.

The quality of this complex power network is critical to the success of a power-gating design. Two of the most critical parameters are the IR-drop and the penalties in silicon area and routing resources. Power gating can be implemented using cell- or cluster-based (or fine grain) approaches or a distributed coarse-grained approach.

Parameters

Power gating implementation has

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