number of in-flight instructions, not SMT. Access to the register file required three pipeline stages due to the physical size of the circuit. Up to eight instructions from four threads could be dispatched to eight integer and four floating-point execution units every cycle. The 21464 had a 64 KB data cache (Dcache), organized as eight banks to support dual-porting. This was backed by an on-die 3 MB, six-way set-associative unified secondary cache (Scache).

The integer execution unit