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an 8 KB unified cache instead of the separate instruction and large data caches like the POWER1. The unified cache is two-way set associative and uses a store-through policy with no reload on a store miss and a least recently used (LRU) replacement policy. It has a cache line size of 64 bytes, and each cache line is sectored into four quadwords (16 bytes), with each quadword given its own valid bit in the cache directory. During each cycle, four words can be read from it

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