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<p>only started supporting Intel's SSE4.1 and SSE4.2 (the full SSE4 instruction set) in the <a href="page.php?w=Bulldozer_%28microarchitecture%29">Bulldozer</a>-based FX processors. With SSE4a the misaligned SSE feature was also introduced which meant unaligned load instructions were as fast as aligned versions on aligned addresses. It also allowed disabling the alignment check on non-load SSE operations accessing memory. Intel later introduced similar speed improvements to unaligned SSE in their Nehalem processors, but did not introduce misaligned</p><p>
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