between transistors, leading to higher-performance devices of greater complexity when compared with earlier nodes. Intel's 65nm process has a transistor density of 2.08 million transistors per square millimeter (MTr/mm2).

Example: Fujitsu 65 nm process

* Gate length: 30 nm (high-performance) to 50 nm (low-power)
* Core voltage: 1.0 V
* 11 Cu interconnect layers using nano-clustering silica as ultralow ? dielectric (?=2.25)

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