<?xml version="1.0" encoding='utf-8'?>
<!DOCTYPE wml PUBLIC "-//WAPFORUM//DTD WML 1.1//EN" "http://www.wapforum.org/DTD/wml_1.1.xml">
<wml>
<card id="card1" title="Asynchronous circuit - Page 7 - Wikipedia">
<p>
<a accesskey="1" href="page.php?w=Asynchronous_circuit&amp;p=6">1.Previous</a><br />
<a accesskey="3" href="page.php?w=Asynchronous_circuit&amp;p=8">3.Next</a>
</p>
<p>of the circuit. This time is called a <a href="page.php?w=propagation_delay">propagation delay</a>.</p>

<p>As of 2021, timing of modern synchronous ICs takes significant engineering efforts and sophisticated <a href="page.php?w=Electronic_design_automation">design automation tools</a>. Designers have to ensure that clock arrival is not faulty. With the ever-growing size and complexity of ICs (e.g. <a href="page.php?w=Application-specific_integrated_circuit">ASICs</a>) it's a challenging task. In huge circuits, signals sent over clock distribution</p><p>
<a accesskey="1" href="page.php?w=Asynchronous_circuit&amp;p=6">1.Previous</a><br />
<a accesskey="3" href="page.php?w=Asynchronous_circuit&amp;p=8">3.Next</a>
</p>

<do type="prev" label="Search">
        <go href="search.wml"/>
</do>

</card>
</wml>
