was driven by these factors:

* Speed: Superficially, the speed of a parallel data link is equal to the number of bits sent at one time times the bit rate of each individual path; doubling the number of bits sent at once doubles the data rate. In practice, clock skew reduces the speed of every link to the slowest of all of the links. However, parallel lines have lower latency than serial lines, which is why parallel lines are still used on memory buses like DDR SDRAM.