<?xml version="1.0" encoding='utf-8'?>
<!DOCTYPE wml PUBLIC "-//WAPFORUM//DTD WML 1.1//EN" "http://www.wapforum.org/DTD/wml_1.1.xml">
<wml>
<card id="card1" title="FIFO (electronic) - Page 8 - Wikipedia">
<p>
<a accesskey="1" href="page.php?w=FIFO_(electronic)&amp;p=7">1.Previous</a><br />
<a accesskey="3" href="page.php?w=FIFO_%28electronic%29&amp;p=9">3.Next</a>
</p>
<p>and write operations, the memory in all asynchronous FIFOs and in many synchronous FIFOs is dual-ported, typically consisting of a <a href="page.php?w=register_file">register file</a> or <a href="page.php?w=dual-ported_RAM">dual-ported RAM</a> (random access memory). In asynchronous FIFOs, the memory is an asynchronous circuit that is accessible to logic operating in any clock domain.</p>

<p><big>Width</big></p>
<p>The data written to and read from a FIFO typically have the same, fixed <a href="page.php?w=word_size">word size</a> (number of <a href="page.php?w=bit">bit</a>s)</p><p>
<a accesskey="1" href="page.php?w=FIFO_(electronic)&amp;p=7">1.Previous</a><br />
<a accesskey="3" href="page.php?w=FIFO_%28electronic%29&amp;p=9">3.Next</a>
</p>

<do type="prev" label="Search">
        <go href="search.wml"/>
</do>

</card>
</wml>
