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<a accesskey="3" href="page.php?w=instruction_pipelining&amp;p=2">3.Next</a>
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<p>In <a href="page.php?w=computer_engineering">computer engineering</a>, <b>instruction pipelining</b> is a technique for implementing <a href="page.php?w=instruction-level_parallelism">instruction-level parallelism</a> within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming <a href="page.php?w=Machine_code">instructions</a> into a series of sequential steps (the eponymous "<a href="page.php?w=Pipeline_%28computing%29">pipeline</a>") performed by different <a href="page.php?w=Central_processing_unit">processor units</a></p><p>
<a accesskey="3" href="page.php?w=instruction_pipelining&amp;p=2">3.Next</a>
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